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NXP S32V234基于64位ARM第二代视频处理器开发方案

2017-11-13 04:03 PM| 发布者: 噗噗东| 查看: 4702| 评论: 0

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nxp公司的S32V234是第二代视频处理器系列,基于64位ARM Cortex-A53CPU,具有高达1000MHz 四核ARM Cortex-A53,集成了32 KB/32 KB I-/D- L1高速缓存,NEON MPE协处理器,双精度FPU,带2 CPU和256KB L2缓存的2集群,存储器管理单元,GIC中断控制器,提供ISP,功能强大的3D GPU,两个APEX-2可视加速器,支持SafeAssure安全性,具有汽车级的可靠性,功能安全性,支持汽车和工业自动化,适用于汽车ADAS,NCAP前置摄像头,物体检测和识别,车载全景可视系统以及机器学习和传感器融合应用.本文介绍了S32V234主要特性,框图,评估板SBC-S32V234主要特性和电路图.

The S32V234 is our 2nd generation vision processor family designed to support computation intensive applications for image processing and offers an ISP, powerful 3D GPU, dual APEX-2 vision accelerators, security and supports SafeAssure.S32V234 is suited for ADAS, NCAP front camera, object detection and recognition, surround view, machine learning and sensor fusion applications. S32V234 is engineered for automotive-grade reliability, functional safety and security measures to support vehicle and industrial automation.

S32V234 has a complete enablement platform supported by S32 Design Studio IDE for Vision which includes a compiler, debugger, Vision SDK, Linux BSP and graph tools.

S32V234主要特性:

• ARM Cortex-A53, 64-bit CPU
C Up to 1000 MHz Quad ARM Cortex-A53
C 32 KB/32 KB I-/D- L1 Cache
C NEON MPE co-processor
C Dual precision FPU
C 2 clusters with 2 CPUs and 256 KB L2 cache each
C Memory Management Unit
C GIC Interrupt Controller
C ECC/parity error support for its memories
C Generic timers
C Fault encapsulation by hardware for redundantexecuted application software on multiple corecluster
• ARM Cortex-M4, 32-bit CPU
C Up to 133 MHz
C 16 KB/16 KB I-/D- L1 Cache
C 32+32 KB tightly coupled memory (TCM)
C ECC/parity support for its memories
• Clocks
C Phase Locked Loops (PLLs)
C 1 external crystal oscillator (FXOSC)
C 1 FIRC oscillator
• System protection and power management features
C Flexible run modes to consume low power based onapplication needs
C Peripheral clock enable register can disable clocks tounused modules, thereby reducing currents
C Power gating of unused A53 cores and GPU
C Low and high voltage warning and detect
C Hardware CRC module to support fast cyclicredundancy checks (CRC)
C 120-bit unique chip identifier
C Hardware watchdog
C eDMA controller with 32 channels (withDMAMUX)
C Extended Resource Domain Controller
• Safety concept
C ISO 26262, ASIL level target
C Measures to detect faults in memory and logic
C Measures to detect single point and latent faults
C Quantitative out of context analysis of functionalsafety (FMEDA) tailored to application specifics
C Safety manual and FMEDA report available
• Security
C CSE with 16 KB of on-chip Secure RAM and ROM.
C ARM TrustZone (TZ) architecture support
C Boot from NOR flash with AES-128 (CTR)
C On-Chip One-Time Programmable elementController (OCOTP_CTRL) with on chip electricalfuse array.
C System JTAG Controller (SJC)
• Debug functionality
C Standard JTAG and Compact JTAG
C 16-bit Trace port, Serial Wire Output port
• Timers
C General purpose timers (FTM)
C Two Periodic Interrupt Timer (PIT)
C IEEE 1588 Timers (part of Ethernet Subsystem)
• Analog
C 1x 12-bit 1.8 V SAR ADC with self-test
• Communications
C UART(w/ LIN2.1l)
C Serial peripheral interface (SPI)
C I2C blocks
C PCI express 2.0 with endpoint and root complexsupport
C LFAST serial link
C 1 GBit Ethernet with PTP IEEE 1588
C FD-CAN
C FlexRay Dual Channel, Version 2.1 RevA
• Memory interfaces
C 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Up to 1066 MHz data rate with ECC (SEC-DEDTED)triple errror detection support for subregion
C QuadSPI supporting Execute-In-Place (XIP)
C Boot flash fault detection and correction using two-dimensional parity.
C Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display
C Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding
C GPU GC3000 with frame buffer compression
C 2x VIU (Video interface unit) for camera input
C 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
C Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions(exposure control, gamma correction)
C 2x APEX2-CL Image cognition processor supporting OpenCL 1.2. APEX-642CL comprises two Array Processing Unit
(APU) cores configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two coreMIMD engines with 32 16-bit CUs each.
C CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter
C JPEG video decoder (8/12-bit)
C H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats
C H.264 video encode (8/10/12-bit), High-intra only
C Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI)
C GPIO pins with interrupt support, DMA request capability, digital glitch filter
C Configurable slew rate and drive strength on all output pins
• System RAM
C 4 MB On-Chip System RAM with ECC

S32V234目标应用:

Automotive
Front View Camera
Smart Rear View Camera
Surround View & Sense Park Assist System
Surround View Park Assist System


图1.S32V234框图

评估板SBC-S32V234

SBC-S32V234: S32V234 Vision and Sensor Fusion Evaluation Board for Prototyping and Development

图2.评估板SBC-S32V234 CRX-S32V载体板框图

图3.评估板SBC-S32V234 MPX-S32V模块框图

图4.评估板SBC-S32V234外形图

图5.评估板SBC-S32V234模块边连接器(载体板CRX-S32V)外形图

图6.评估板SBC-S32V234非模块边连接器(载体板CRX-S32V)外形图

图7.评估板SBC-S32V234模块(MPX-S32V)外形图(正面)

图8.评估板SBC-S32V234模块(MPX-S32V)外形图(背面)
评估板SBC-S32V234主要特性:




图9.评估板SBC-S32V234电路图(1)

图10.评估板SBC-S32V234电路图(2)

图11.评估板SBC-S32V234电路图(3)

图12.评估板SBC-S32V234电路图(4)

图13.评估板SBC-S32V234电路图(5)

图14.评估板SBC-S32V234电路图(6)

图15.评估板SBC-S32V234电路图(7)

图16.评估板SBC-S32V234电路图(8)

图17.评估板SBC-S32V234电路图(9)

图18.评估板SBC-S32V234电路图(10)

图19.评估板SBC-S32V234电路图(11)

图20.评估板SBC-S32V234电路图(12)

图21.评估板SBC-S32V234电路图(13)
详情请见:
https://www.nxp.com/docs/en/data-sheet/S32V234_data_sheet_Rev3.1.pdf
和https://www.nxp.com/docs/en/user-guide/SBC-S32V_User_Manual.pdf
以及https://www.nxp.com/downloads/en/schematics/SCM-MPX-S32V234-R2.pdf


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