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TI 66AK2L06 KeyStoneSoC DSP系统开发方案

2017-11-24 08:04 PM| 发布者: admin| 查看: 1335| 评论: 0

摘要: TI公司的66AK2L06 KeyStoneSoC是{方案}KeyStone II Multicore SoC架构的C66x系列产物,集成了多种子系统(ARM CorePac, C66x CorePacs, IP网络,数字前端,FFT处理),器件中的ARM和DSP核提供了极好的信号和控制处理性能, ...

TI公司的66AK2L06 KeyStoneSoC是{方案}KeyStone II Multicore SoC架构的C66x系列产物,集成了多种子系统(ARM CorePac, C66x CorePacs, IP网络,数字前端,FFT处理),器件中的ARM和DSP核提供了极好的信号和控制处理性能,主要用在医疗电子,测试丈量,航空电子和军事以及工业控制.本京电港论坛文章先容了66AK2L06主要特点,框架图,以及66AK2L06 JESD Attach to ADC12J4000 / DAC38J84设计主要特性,系统框图,电路原理图纸和质料清单.

The 66AK2L06 KeyStoneSoC is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.

66AK2L06主要特性:

Four TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core
38.4 GMacs/Core for Fixed Point @ 1.2 GHz
19.2 GFlops/Core for Floating Point @ 1.2 GHz
Memory
32K Byte L1P Per CorePac
32K Byte L1D PerCorePac
1024K Byte Local L2 Per CorePac
ARM CorePac
Two ARM® Cortex®-A15 MPCore™ Processors at Up to 1.2 GHz
1MB L2 Cache Memory Shared by Two ARM Cores
Full Implementation of ARMv7-A Architecture Instruction Set
32KB L1 Instruction and Data Caches per Core
AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low Latency Access to Shared MSMC SRAM
Multicore Shared Memory Controller (MSMC)
2 MB SRAM Memory Shared by Four DSP CorePacs and One ARM CorePac
Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
On-chip Standalone RAM (OSR) - 1MB On-Chip SRAM for Additional Shared Memory
Hardware Coprocessors
Two Fast Fourier Transform Coprocessors
Support Up to 1200 Msps at FFT Size 1024
Support Max FFT Size 8192
Multicore Navigator
8k Multi-Purpose Hardware Queues with Queue Manager
Packet-Based DMA for Zero-Overhead Transfers
Network Coprocessor
Packet Accelerator Enables Support for
1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second
Security AcceleratorEngine Enables Support for
IPSec, SRTP, and SSL/TLS Security
ECB, CBC, CTR, F8,CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, SHA-1, SHA-2 (256-bit Hash), MD5
Up to 6.4 GbpsIPSec
Ethernet Subsystem
Peripherals
DigitalFront End (DFE) Subsystem
Support up to Four Lane JESD204A/B (7.37 Gbps Line Rate Max.) Interface to Multiple
Data Converters
Integration of Digital Down/Up-Conversion (DDC/DUC) Module
IQNet Subsystem
Transporting data streams to an integrated Digital Front End (DFE)
Two One-Lane PCIe Gen2 Interfaces
Supports Up to 5 GBaud
Three Enhanced Direct Memory Access (EDMA) Controllers
72-Bit DDR3 Interface, Speeds Up to 1600 MHz
EMIF16 Interface
USB 3.0 Interface
USIM Interface
Four UART Interfaces
Three I2C Interfaces
64 GPIO Pins
Three SPI Interfaces
Semaphore Module
Fourteen 64-Bit Timers
Commercial Case Temperature:
0℃ to 100℃
Extended Case Temperature:
C40℃ to 100℃
66AK2L06主要应用:
Medical
Test and Measurement
Avionics and Defense
Industrial

图1{京电港论坛}. 66AK2L06框图

66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计

TI Designs provide the foundation that you need including methodology, testing and design files quickly evaluate and customize the system. TI Designs help you accelerate your time to market.

The 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide demonstrates performance of the high-speed JESD204B connectivity between the 66AK2L06 System-on-Chip (SoC) with industry-leading high-speed data convertors. This design also demonstrates the signal-processing power of 66AK2L06 hardware co-processors, DSP CorePacs, and control processing power using ARM® CorePacs. A highlevel hardware block diagram shown in Figure 3 explains high-level connectivity of the 66AK2L06 device with ADC12J4000 and DAC38J84 for different applications. Here, the analog input comes from an ADC that best matches the requirements of each industry application. The analog input will be sampled, digitized, and sent to the 66AK2L06 device over a JESD interface. The 66AK2L06 processes the received data using its internal hardware co-processors and sends the data out via any of the available interfaces including JESD, Ethernet, or PCIe. The JESD output from the 66AK2L06 can be sent over the JESD interface to DAC38J84 for converting digitized data to analog output.

The 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design is well suited for applications such as:

• Communications test: Mobile handset testers, radio communication analyzer, base station analyzer, RF test cards
• General purpose test: Spectrum analyzers, vector or signal analyzer, vector or signal generator, oscilloscopes
• High-speed data acquisition and generation
• Electronic warfare and communications: Military radar, civilian radar, synthetic-aperture radar (SAR), signals Intelligence (SIGINT / ELINT), countermeasure
• Missiles and ground defense: Missile guidance and control systems, missile compute platforms, monitoring systems
• Military aircraft and general aviation: Unmanned systems, munitions, surveillance or mobility aircraft

66AK2L06 JESD Attach to ADC12J4000 / DAC38J84设计特性:

• Easy Integration Of Signal Processor To Data Converters Over JESD204B
• Multichannel Sampling Rates Up To 368 Msps With 120 MHz Of Processing Bandwidth
• DFE Processing For Filtering, Down-sampling, Or Up-sampling
• System Optimized For Test And Measurement And Defense Applications
• Wideband Sampling With JESD Attached Signal  Processing Solution Including DSP™, ADC And DAC Boards, Demo Software, Configuration GUIs, And Getting Started Guide
• A Robust Demonstration And Development Platform Including Three EVMs, A Deterministic
Latency Card, Schematic, BOM, User Guide, Benchmarks, Software, And Demos

特性应用:

• Test And Measurement
• Defense

图2{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计开辟套件外形实物图
66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Design Development Kit

图3{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计系统框图

图4{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计系统硬件毗连图

图5{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计系统电路框图

图6{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(1)

图7{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(2)

图8{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(3)

图9{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(4)

图10{京电港论坛}. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(5)

图11. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(6)

图12. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(7)

图13. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(8)

图14. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(9)

图15. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(10)

图16. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(11)

图17. 66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计电路图(12)
66AK2L06 JESD Attach to ADC12J4000/DAC38J84设计材料清单:


详情请复制打开此衔接所在:
http://www.ti.com/lit/ug/tidu946/tidu946.pdf
和http://www.ti.com/lit/df/tidrek6/tidrek6.pdf
以及http://www.ti.com/lit/df/tidrek7/tidrek7.pdf


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